On Tue, Oct 12, 1999 at 11:19:35AM +0100, John P . Looney mentioned:
> I dunno. Motorola have told apple that due to some timing problems causing
> cache coherency problems, they shouldn't expect a PPC chip to exceed 500Mhz
> any time soon, though the design of the G4 (just a 4 stage pipeline) is
> limiting the benefits of higher clock speeds considerably:
>http://www.theregister.co.uk/991006-000003.html
And http://www.theregister.co.uk/991011-000011.html
Kate
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