[OT] CISC vs RISC [was Re: [ILUG] impressive...]

[Jakma, Paul]

> IIRC, the PALcode is more like "here are commonly used
> subroutines that are used by the OS, let's shove them right
> down into the CPU itself".  Different OSes load different PALcode
> at boot time.
> 

i don't have much info on it, but i was under the distinct impression that
it's more low-level than common os routines. ie i thought it was something
that defined exactly how an instruction worked, aswell as providing cpu
specific extension instructions like perf. counters, hardware debug
facilities.. etc. 

but i've never really read up on it.. (and as i see below, i'm a bit wrong).

> I guess that it's done to avoid the overhead of a full-blown
> interrupt or exception to handle certain things.  For example,
> VMS on Alpha uses PALcode to help implement ASTs,
> for which there was hardware support in the VAX architecture.
> 

ah ok... intterupt handling was something i thought would be helped along by
PALcode. However i thought it was that PAL defined internal CPU handling,
rather than being a convenient on-chip library. (i've already read below)

> Alpha instructions themselves are _not_ implemented in 
> PALcode. PALcode is written in Alpha instructions and
> called via some sort of CallPALRoutine instruction.
> 

ok.. that's cleared up a huge misconception of mine then! :)
So Alpha really is a pure RISC design...

> Must get my hands on an Alpha Architecture Manual...
> Paul, got any lying around the office that nobody wants?? :-)
>

doubt it very much. It's not online either, although we do have the ISBN
number online, so you could try amazon. If you ever get your hands on one:
bags seconds!
 
> Later,
> Kenn

-paul.