[ILUG] Optimizing for Pentium Pt.2

[Paul Kelly]

John Gay wrote:
> looking into these things. As Isaid, the PGCC site does not seem to have been 
> updated in at least a year or more?!? I am also looking into GCC itself. Now 
> that the 3.1. series is out, it might be better than when the PGCC patches 
> were written

gcc has been as good as or better than pgcc for quite a while. pgcc was 
was written back in the days when gcc splintered due to a perception of 
slow progress on the main branch. A number of Linux distributions wound 
up using egcs, partly derived from the pgcc work as I recall. Happiness 
was restored to the world with gcc 2.95 and later.

 > The bottom line is, Pentiums have better instruction sets than
> the original 386 instructions that they still support.

Not really, no. The only instruction of consequence (to gcc anyway) 
since the i386 was the CMOV introduced with the Pentium Pro. gcc 2.95 
will use that instruction if directed to with -march=pentiumpro and you 
will generally get a few percent improvement out of it. Code compiled 
with that option will fail on Pentium and earlier processors.

> The Pentium also 
> started introducing pipelining so properly generated code can be upto 30% 
> faster than equivulent code that performs the same function!

That's the art of instruction scheduling - rearranging the instructions 
generated by the compiler such that they make best use of the parallel 
("superscalar") pipelines present in a modern CPU. gcc 2.95 has a fair 
go at scheduling according to the -mcpu=pentium/pentiumpro option. gcc 
3.1 does a better job, and fine tunes for a few more processors such as 
athlon and athlon-xp. They're in the process of replacing the compiler's 
instruction scheduling with a whole new mechanism that should do an even 
better job, but that's a ways down the road yet in gcc 3.3.

As for the exotic extra instructions sets, gcc 3.1 will make use of SSE 
or SSE2 instructions instead of 387 instructions if you use the 
-mfpmath=sse option and you may see some speed benefit from it, but 
there's a chance you may also see incompatibilities. gcc will still use 
i387 code for missing functionality in the SSE instruction set (double 
precision floats for example).

AFAIK no current gcc will ever use MMX or 3DNOW! instructions though gcc 
3.1 enables user code to explicitly generate these instructions with C 
code. The kernel sometimes uses these instruction sets to get super-fast 
block copies of memory or RAID math but not much else.

> Not sure what improvements the P4 introduce? I think it's mostly just speed 
> improvements rather than any execution changes.

P4 introduced SSE2, a _MUCH_ improved version of SSE and a viable 
replacement for i387 FPU code. SSE supports only single precision floats 
while SSE2 can handle doubles. MMX and SSE shared registers with the FPU 
which hobbles them a bit, but SSE2 has its own large, dedicated register 
file. So far P4 is the only CPU equipped with SSE2. AMD's x86-64 CPUs 
are said to have it as well. Of course x86-64 itself is a whole other 
ball game...

Paul.