On Thu, 9 Sep 2004, Eoin Ryan wrote:
> Hi Everyone,
>> We have a rack of Dell Poweredge 750's which we use as processing nodes
> for scientific experiments. The CPU's are P4s with HT. Currently, the
> 2.6.8-smp kernel is running on the cluster, so /proc/cpuinfo sees each
> machine as having 2 processors.
Almost certainly switch it off.
There's a very good Ars Technica discussion on this (didn't bookmark it,
Basically Intel invented HT because they were screwed - the P4 is much
less efficient (waffle figure 30%) less than the P3 at the same clock.
The P4 has a really deep pipeline - lots of instructions on the go (ISTR
it's 20, shortly to rise to 30 stages). Lots of short stages means the
clockspeed can be pushed right up.
Lots of stages also means the chip needs to know what's going a long way
ahead, and it frequently doesn't, so has to insert "bubbles" into the
Intel's answer was to create *two* feeds into the mouth of the pipe, to
keep it fed with useful work. From the outside, it looks like two
processors, but if you get at most a 30% speed advantage, and only if the
two threads aren't trying to do the same kind of work.
If your code is million-iteration floating point loops, the FPU will be
running at full efficiency, and no other tweaking will budge your
And switching HT on does impose some bureaucratic overhead to avoid the
instruction streams from getting mixed up, and this is supposed to be a
penalty of a few percentage points.
I manage Xeon machines currently being used for Monte Carlo simulations -
a few short tests showed that HT on definitely wasn't better, might be
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