From: Liam Bedford (lbedford at domain lbedford.org)
Date: Wed 20 Jun 2001 - 17:16:05 IST
On Wed, Jun 20, 2001 at 04:53:52PM +0100, Niall O Broin came forth with:
> On Wed, Jun 20, 2001 at 11:37:46AM +0100, Paul Jakma wrote:
> > > Other minor detail is that no AMD processor currently available in this
> > > country can be used in a SMP configuration.
> > it's not the cpu, it's the chipset. Athlon would work fine if someone
> > built a chipset that supported SMP (see below). Indeed, K6 would
> > "support" SMP too.
> I always understood that CPUs had to be specially designed to handle MP. At
> the very least isn't cache coherency an issue (I suppose the chipset could
> invalidate cache pages somehow, but I've always heard about MP capable
> chips, so I presumed that chips had to be specially designed. How, for
> instance, do they handle the fact that they can't access memory ad lib ?)
But all the AMD processors have supported MP for ages, just no-one has
released a chipset that supported it.
As Paul said, the K6 could have been multi-processor if someone
had made the OpenAPIC chipset (or whatever the acronym of the week was)
-- Liam Bedford | Four thousand holes in Blackburn, Lancashire Software Engineer | And though the holes were rather small WBT Systems, Block 2, | They had to count them all Harcourt Centre, Harcourt St. | Now they know how many holes it takes to fill 01-4170100 | The Albert Hall
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