RE: [ILUG] hardware question

From: HAMILTON,DAVID (HP-Ireland,ex2) (david_hamilton3 at domain hp.com)
Date: Wed 20 Jun 2001 - 17:19:12 IST


Niall,

You are correct in most of this. The following paragraph is from AMD's web
site:

A key advantage of AMD's multiprocessing platform is Smart MP technology,
which greatly enhances overall platform performance by increasing data
movement between the two CPUs, chipset and memory system. Smart MP
technology features dual point-to-point, high-speed 266MHz system buses with
Error Correcting Code (ECC) support designed to provide up to 2.1GB per
second per CPU of bus bandwidth in a dual-processor system. Smart MP
technology also has an optimized Modified Owner Exclusive Shared Invalid
(MOESI) cache coherency protocol that manages data and memory traffic in a
multiprocessing environment.

As you can see, the new chips have been optimised and modified in order to
function reliably and efficiently in a MP environment.

        David.

David Hamilton
Senior Technical Consultant
HP Ireland

-----Original Message-----
From: Niall O Broin [mailto:niall at domain linux.ie]
Sent: 20 June 2001 16:54
To: ILUG (E-mail)
Subject: Re: [ILUG] hardware question

On Wed, Jun 20, 2001 at 11:37:46AM +0100, Paul Jakma wrote:

> > Other minor detail is that no AMD processor currently available in this
> > country can be used in a SMP configuration.
>
> it's not the cpu, it's the chipset. Athlon would work fine if someone
> built a chipset that supported SMP (see below). Indeed, K6 would
> "support" SMP too.

I always understood that CPUs had to be specially designed to handle MP. At
the very least isn't cache coherency an issue (I suppose the chipset could
invalidate cache pages somehow, but I've always heard about MP capable
chips, so I presumed that chips had to be specially designed. How, for
instance, do they handle the fact that they can't access memory ad lib ?)

Regards,

Niall "Not much of a CPU designer" O Broin

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