From: Paul Jakma (paulj at domain alphyra.ie)
Date: Wed 20 Jun 2001 - 20:09:21 IST
On Wed, 20 Jun 2001, Niall O Broin wrote:
> I always understood that CPUs had to be specially designed to
> handle MP. At the very least isn't cache coherency an issue (I
> suppose the chipset could invalidate cache pages somehow, but I've
> always heard about MP capable chips, so I presumed that chips had
> to be specially designed.
educated guessing:
well, for any kind of modern system with a cache and a bus controller
that can do DMA (eg ISA, PCI, presumably VLB) there probably is a way
for the chipset to invalidate cache on the CPU - it's just the easy
thing to do i'd think.
or the chip has to snoop the local bus and invalidate it's cache as
it sees fit. in which case you might design a chipset to fake memory
accesses. (read, write back, yuk, yuk)
finally, there might be no hardware cache coherency provisions at all.
in which case it's up to the OS to handle it. Eg, there's at least one
if not a few MIPS chips like that - eg either R12k or R10k iirc¹. And
afaik there are SMP R12k and definitely R10k IRIX boxes. (iirc linux
assumes a certain level of cache coherency and so will probably never
work on this chip. comes up every now and then on linux-mips)
> How, for instance, do they handle the
> fact that they can't access memory ad lib ?)
but they don't anyway. there's always something between the CPU and
DRAM. At the very least address decoders and refresh circuitry.. and
more typically on anything above embedded CPUs, a complex chip.
so you arbitrate invisibly there. not a major problem in itself unless
the cpu is somehow really tightly coupled timing wise to address
decoders or worse RAM. (wouldn't be much of a general purpose
processor then though, be pretty weird).
DEC pyxis (21174) and presumably the SMP derivative controllers for
the 21164s CPUs, switched the CPU straight to RAM (well address
decoders) whenever possible.
i'm no way an expert but main point is that, AFAICT, unless a chip is
specifically designed to be purposely awkward and implement really
weird shit to almost specifically make SMP impossible, you can design
a chipset to do it.
> Niall "Not much of a CPU designer" O Broin
--paul "picked up enough terminology from lists and books to hopefully
be able to bullshit you" j
:)
¹ have to check this from home.
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