From: Paul Jakma (paul at domain clubi.ie)
Date: Thu 21 Jun 2001 - 00:35:11 IST
On Wed, 20 Jun 2001, Paul Jakma wrote:
> finally, there might be no hardware cache coherency provisions at all.
> in which case it's up to the OS to handle it. Eg, there's at least one
> if not a few MIPS chips like that - eg either R12k or R10k iircą. And
> afaik there are SMP R12k and definitely R10k IRIX boxes. (iirc linux
> assumes a certain level of cache coherency and so will probably never
> work on this chip. comes up every now and then on linux-mips)
the RM7000 lacks cc completely. the R10k has some issues, esp on the
O2 and I2, to do with processor 'features' and interaction with the
system controllers - but i don't really understand it..
regards,
-- Paul Jakma paul at domain clubi.ie paul at domain jakma.org PGP5 key: http://www.clubi.ie/jakma/publickey.txt ------------------------------------------- Fortune: The wages of sin are high but you get your money's worth.
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