From: Paul Jakma (paulj at domain alphyra.ie)
Date: Wed 15 Aug 2001 - 19:35:44 IST
On Wed, 15 Aug 2001, Liam Bedford wrote:
> correct way to do what? make it 56 would be
> br label
> mov 56, r1
so executing the instruction after the branch is normal? what's the
rule for that?
is it something to do with groupings, eg having to make sure by hand
that dependent instructions are far enough 'away' from the previous
instruction to not be executed at the same time, ie every set of,
say, 2 ops are executed in parallel???
> It seems to be a standard thing for RISC machines, and if you're taking
> x86/m68k code, you can just shove a NOP after the branch (but you waste a
> lot of speed).
ah... gcc spits out /lots/ of NOPs on MIPS. :(
in a way i guess it is a pain for asm writers. however, shifting all
that complexity out of the CPU core and into software was the whole
point of RISC in the first place. so from that POV it is very very
(but then with MIPS R4kish and up they started to add more and more
speculation logic back into the CPUs... even the original RISC chip
wasn't immune to featuritis).
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